Top Level Tab - 1.2 English - PG351

HDMI 2.1 Receiver Subsystem v1.2 Product Guide (PG351)

Document ID
PG351
Release Date
2025-11-20
Version
1.2 English

The following figure shows the top level tab.

Figure 1. Top Level Tab Generated by Your Tool

The parameters on the top level tab are as follows.

Component Name
Set automatically by the IP integrator.
Video Interface
Selects the video interface for the HDMI 2.1 RX Subsystem. The allowable options are AXI4-Stream, Native Video, and Native Video (Vectored DE).
Include HDCP Encryption
Enables both HDCP 1.4 and 2.3 encryption.
Note: HDCP Encryption options are only configurable if you have a HDCP license; otherwise it is disabled and grayed out from the GUI.
HDMI 2.x Mode
Selects the HDMI 2.x Mode for the HDMI 2.1 RX Subsystem. The allowable options are HDMI 2.1 (FRL + TMDS) and HDMI 2.1 (TMDS ONLY).
Enable Dynamic HDR Support
Enables Dynamic HDR support (Section 10.10.2.3 of the HDMI 2.1 specification (https://www.hdmi.org/spec/hdmi2_1)).
DSC Enable
Enables DSC passthrough support.
Important: External YUV420 Conversion is removed. Optimized AXIS Remapper and YUV 420 Conversion is added inside the subsystem. External Video AXI4S Remapper is not required in designs for 8kp60/10kp60 support. To enable 8kp48, 8kp50, 8kp60/10kp60 YUV420, select Number of pixels per clock as 8. Otherwise, it is recommended to select Number of pixels per clock as 4, which is sufficient to support up to 8k/10kp30.
Important: In Native Video or Native Video (Vectored DE) interface, the IP supports YCbCr 4:2:0. However, you must process YCbCr 4:2:0 Pixel Encoding. See Section 7 in the HDMI 2.0b Specification (https://www.hdmi.org/spec/index) or AXI4-Stream Video Output Stream Interface.
Max bits per component
Selects the maximum bits per component. The allowable options are, 8, 10, 12, or 16 bits. This parameter is to set the maximum "allowed" bits per component, and the actual bits per component can be set from the software API to a different value. However, the actual bits per component is bounded by the Max bits per component. For example, if the Max bits per component is set to 16, you can set the actual bits per component from the software API to any of the values, 8, 10, 12, or 16. But if the Max bits per component is set to 8, you can only set the actual bits per component to 8 through the software API.
Number of pixels per clock on Video Interface
Selects the number of pixels per clock. The allowable options are 4 or 8 pixels per clock in the AXI4-Stream Interface. Native Video or Native Video (Vectored DE) Interface supports only 4 pixels per clock.
Note: The IP supports only resolutions that are divisible by 4 (HTotal, HActive, and HBlank). For YUV 420, only video timings that are divisible by 8 are supported.
Number of GT lanes
Fixed to 4 GT lanes.
Hot Plug Detect Active
Selects the HPD active polarity. The allowable options are High or Low.
EDID RAM size
The allowable options are, 256, 512, 1024, or 4096.
Cable Detect Active
Selects the Cable Detect active polarity. The allowable options are High or Low.