| hpd |
O
|
1 |
If XGUI option: Hot Plug Detect active-High
(Default)
- 0: Hot Plug Detect is released
- 1: Hot Plug Detect is asserted
If XGUI option: Hot Plug Detect
active-Low
1
- 0: Hot Plug Detect is asserted
- 1: Hot Plug Detect is released
|
| cable_detect |
I |
1 |
If XGUI option: Cable Detect active-High
(Default)
- 0: Cable Detect is released
- 1: Cable Detect is asserted
If XGUI option: Cable Detect active-Low
2
- 0: Cable Detect is asserted
- 1: Cable Detect is released
|
| irq |
O |
1 |
Interrupt request for CPU. Active-High. |
| frl_clk
5
|
I |
1 |
Fixed FRL link clock. |
| video_clk |
I |
1 |
Reference Native Video Clock
The HDMI 2.1 RX core uses this
video_clk to clock out the Video Data together with the
video_cke_out. Then an Video In to AXI4-Stream Bridge module is added to the HDMI 2.1 RX Subsystem to convert Native
Video into AXI4-Stream
Video.
|
|
video_cke_out
5
|
O
|
1 |
Video clock enable signal FRL
Mode: video_cke_in is used to synchronize the video data rate of
the HDMI TX core with the
HDMI RX core in cases
where a frame buffer is not used. This port is not intended to
be used with systems using a frame buffer or data source other
than the HDMI RX Core.
HDMI RX Core
video_cke_out must be connected to video_cke_in. Make sure
video_cke_out from the HDMI
RX core is synchronized to the HDMI TX clock domain; see the passthrough example
design for an example on how this is implemented.
TMDS Mode: Not used
|
| SB_STATUS_IN_tdata |
I |
8 |
Side Band Status input signals
- Bit 0: link_rdy
- Bit 1: video_rdy
- Bits [7:2]: Reserved
|
| SB_STATUS_IN_tvalid |
I |
1 |
Side Band Status input valid |
| fid
3
|
I |
1 |
Field ID for AXI4-Stream bus. Used only for interlaced video.
- 0: Even field
- 1: Odd field
This bit is sampled coincident with the SOF
on the AXI4-Stream bus.
If the signal is not used, set the input to Low.
|
| video_rst
4
|
O |
1 |
Video reset signal in video_clk domain. Active-High. |
- The Hot Plug Detect (HPD) signal is driven
by an HDMI sink and asserted when the HDMI cable is connected to notify the HDMI source of the presence of an HDMI sink. When designing an HDMI sink system using the HDMI 2.1 RX Subsystem, in the PCB,
if you choose to use a voltage level shifter, the HPD
polarity remains as active-High. However, if you choose to
add an inverter to the HPD signal, then the HPD polarity
must be set to active-Low in the HDMI 2.1 RX Subsystem GUI. There are two common ways
of using HPD: Toggle HPD to trigger HDCP authentication
process (usually 100 ~ 500 ms). Or a longer HPD toggle
(>1s), the HDMI sink is notifying the
source its present without cable unplug and plug. The
software API used to assert and release HPD is
XV_HdmiRxSs1_SetHpd.
- The Cable Detect signal connects to a 5V
power signal from the HDMI
cable connector through some level shifter to notify the
HDMI 2.1 RX Subsystem that
an HDMI source is
connected.
- Applicable only when the AXI4-Stream video interface
present.
- Applicable only when the Native Video or
Native Video (Vectored DE) interface present.
- The frl_clk and video_cke_out signals only display when the
HDMI 2.x Mode (C_HDMI_MODE) option is set as HMDI 2.1 (FRL +
TMDS).
- The video_cke_out
pulse is high for 1/4 of the video_clk period (equivalent to
TMDS clock/4 in TMDS Mode).
In FRL Mode,
the TX embeds audio, video, AUX, and timing data as TMDS
Tri Bytes into the FRL stream. The video_cke_out signal
goes high whenever a TMDS Tri Byte is present in the FRL
stream. This signal is currently used for video clock
recovery in pass-through for FRL mode, and can also be
used to determine fractional or integer frame
rate.
For example, for 1080p60
video in FRL 12G, video_cke_out is high for
(148,500,000/4) = 37,125,000 clocks per second (measured
in the video_clk domain). You can multiply the measured
video_cke_out frequency by 4 to obtain the video clock
frequency, then divide by Htotal x Vtotal to derive the
frames per second.
|