Register Space - Register Space - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document_ID
PG347
Release_Date
2026-07-31
Version
3.4 English

You can access the register space when AXI Slave Bridge mode is enabled (based on GUI settings). You can also access Bridge registers in Controller0 or in Controller1 and can also access Host memory space. Host memory address offset varies based on Contoller0 and/or Controller1 selection.

If only Contoller0 is enabled, the table below shows address ranges and limitations.

Table 1. AXI Slave Bridge Register Space for Controller0
Register Space AXI Slave Interface Address Range Details
ECAM space 0x6_0000_0000 - 0x6_0FFF_FFFF ECAM is described in Enhanced Configuration Access Memory Map.
Bridge registers 0xFCE2_0000 - 0xFCE2_7FFF Bridge registers are not accessible from PL area. Bridge register can be access through APB access; see Versal Adaptive SoC Register Reference (AM012).
Slave Bridge access to Host memory space 0xE000_0000 - 0x EFFF_FFFF

0x6_1101_0000 - 0x7_FFFF_FFFF

0x80_0000_0000 - 0xBF_FFFF_FFFF

 This address space is valid when only controller 0 is enabled.

0xE000_0000 - 0xE7FF_FFFF

0x6_1101_0000 - 0x6_FFFF_FFFF

0x80_0000_0000 - 0x9F_FFFF_FFFF

 This address space is for controller 0 when both controller 0 and 1 are enabled.

The table below shows address ranges and limitations for when Contoller1 is enabled.

Table 2. AXI Slave Bridge Register for Contoller1
Register Space AXI Slave Interface Address range Details
ECAM space 0x6_0000_0000 - 0x6_0FFF_FFFF ECAM is described in Enhanced Configuration Access Memory Map.
Bridge registers 0xFCEA_0000 - 0xFCEA_7FFF Bridge registers are not accessible from PL area. Bridge register can be access through APB access; see Versal Adaptive SoC Register Reference (AM012).
Slave Bridge access to Host memory space 0xE800_0000 - 0xEFFF_FFFF

0x7_1101_0000 - 0x7_FFFF_FFFF

0xA0_0000_0000 - 0xBF_FFFF_FFFF

 Address range for Slave bridge access is set during IP customization in the Address Editor tab of the Vivado IDE.

When both Contoller0 and Controller1 are enabled, the table above remains same for Controller1.

Bridge register descriptions are found in cpm5-qdma-v4-0-bridge-registers.csv available in the register map files. These register space details are also available in Versal Adaptive SoC Register Reference (AM012).

To locate the register space information:

  1. Download the register map files.
  2. Extract the ZIP file contents into any write-accessible location.
  3. Refer to the cpm5-qdma-v4-0-bridge-registers.csv file.