Port Descriptions - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document ID
PG347
Release Date
2025-12-03
Version
3.4 English

AMD Versal™ device CPM5 has two QDMA IPs, which can be selected in the AMD Vivado™ IP customization GUI.

  • Controller 0 QDMA (QDMA0)
  • Controller 1 QDMA (QDMA1)

Based on the GUI selection, QDMA0 or QDMA1 ports will be enabled. Ports described below have a prefix of dma<n>_, which can be dma0_ for QDMA Port 0 or dma1_ for QDMA Port 1.

Note: Ports without prefix dma0_ or dma1_ are global ports.
Table 1. Parameters
Parameter Name Description
PL_LINK_CAP_MAX_LINK_WIDTH Phy lane width
C_M_AXI_ADDR_WIDTH AXI4 Master interface Address width
C_M_AXI_ID_WIDTH AXI4 Master interface id width
C_M_AXI_DATA_WIDTH

AXI4 Master interface data width

512 bits
C_S_AXI_ID_WIDTH AXI4 Bridge Slave interface id width
C_S_AXI_ADDR_WIDTH AXI4 Bridge Slave interface Address width
C_S_AXI_DATA_WIDTH

AXI4 Bridge Slave interface data width

512 bits
C_S_AXI_ID_WIDTH AXI4 Bridge Slave interface id width
AXI_DATA_WIDTH

AXI4 DMA transfer data width

512 bits