Mailbox IP Address Offset - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2025-12-03
Version
3.4 English

Mailbox IP is accessible from PF and VF functions based on the bar address offsets. Bar offsets are different for different PF and VF functions. Set the address bit[64:32] to 0x208 to be recognized as a mailbox transfers.

Address bit[30] decides PF or VF

  • 1'b0 : PF
  • 1'b1 : VF

When bit[30] = 0

PF address offset bits are [27:26]

  • 2'b00 : PF0
  • 2'b01 : PF1
  • 2'b10 : PF2
  • 2'b11 : PF3

When bit[30] = 1

VF address offset bits are [27:26]

  • 2'b00 : VF0
  • 2'b01 : VF1
  • 2'b10 : VF2
  • 2'b11 : VF3

Set pcie_qdma_mailbox IP address "Master base address" as 0x208_0000_0000 and "Range" for 2G in "Address editor". For more information, see Versal_CPM_QDMA_EP_Design.