MSIX Interrupt Options - 3.4 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2024-05-30
Version
3.4 English

The following table describes the possible scenarios and outcomes:

Table 1. MSIX Interrupt Options
MSIX Enable (MSIX capability) MSIX Mask (MSIX capability) Mask Per Vector (in MSIX table) usr_irq_ack/Fail Outcome Interrupt at Host
0 0 0 usr_irq_fail asserted Not Received
0 0 1 usr_irq_fail Not Received
0 1 0 usr_irq_fail Not Received
0 1 1 usr_irq_fail Not Received
1 0 0 usr_irq_ack Received
1 0 1 usr_irq_ack with PBA bit set Not Received
1 1 0 usr_irq_ack with PBA bit set Not Received
1 1 1 usr_irq_ack with PBA bit set Not Received