The interface signals for the Bridge are described in the following table.
| Signal Name | I/O | Description |
|---|---|---|
| gt_refclk0_p/gt_refclk0_n | I | GT reference clock. |
| pci_gt_txp/pci_gt_txn [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | O | PCIe TX serial interface. |
| pci_gt_rxp/pci_gt_rxn [PL_LINK_CAP_MAX_LINK_WIDTH-1:0] | I | PCIe RX serial interface. |
| pcie0_user_lnk_up | O | Output active-High identifies that the PCI Express core is linked up with a host device. |
| pcie0_user_clk | O | User clock out. PCIe derived clock output for all interface signals output/input to AXI Bridge. Use this clock to drive inputs and gate outputs from AXI Bridge. |
| dma0_user_reset | O | User reset out. AXI reset signal synchronous with the clock provided on the pcie0_user_clk output. This reset should drive all corresponding AXI Interconnect signals. |
| cpm_cor_irq | O | Reserved |
| cpm_misc_irq | O | Reserved |
| cpm_uncor_irq | O | Reserved |
| cpm_irq0 | I | Reserved |
| cpm_irq1 | I | Reserved |