GTYP Quad and REFCLK Placements - GTYP Quad and REFCLK Placements - 3.4 English

GTYP Quad and REFCLK Placements - GTYP Quad and REFCLK Placements - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document_ID

PG347

Release_Date

2026-07-31

Version

3.4 English

The allowable GTYP quad placements are shown in the following table. Placements are determined by CIPS IP configuration GUI as part of CPM configuration selections.

Table 1. Allowable GTYP Quad Placement - Production Silicon
Board	CPM5 PCIe Controller Width Configuration		GTYP Transceiver Quad (Package Bank) Channels																CPM5 PCIe Controller GTYP Reference Clock		Other Supported Width Configurations	Lane Reversal
	Controller 1	Controller 0	Quad 3 (Bank 105)				Quad 2 (Bank 104)				Quad 1 (Bank 103)				Quad 0 (Bank 102)				CPM5 PCIe Controller GTYP Reference Clock
	Controller 1	Controller 0	3	2	1	0	3	2	1	0	3	2	1	0	3	2	1	0	Controller 1	Controller 0
x16	–	x16	Controller 0 [0:15]																–	Quad 104, REFCLK 0	x8, x4	Not Required
x8, x8	x8	x8	Controller 1 [0:7]								Controller 0 [0:7]								Quad 104, REFCLK 0	Quad 102, REFCLK 0	x8, x4 x4, x8 x4, x4	Not Required
x8	x8	–	Controller 1 [0:7]								–								Quad 104, REFCLK 0	–	x4	Not Required
x8	–	x8	–								Controller 0 [0:7]								–	Quad 102, REFCLK 0	x4	Not Required
x4, x4	x4	x4	–				Controller 1 [3:0]¹				–				Controller 0 [3:0]¹				Quad 104, REFCLK 0	Quad 102, REFCLK 0	–	On PCB
x4	x4	–	–				Controller 1 [3:0]¹				–								Quad 104, REFCLK 0	–	–	On PCB
x4	–	x4	–								–				Controller 0 [3:0]¹				–	Quad 102, REFCLK 0	–	On PCB
x4, x8	x4	x8	–				Controller 1 [3:0]¹				Controller 0 [0:7]								Quad 104, REFCLK 0	Quad 102, REFCLK 0	x4, x4	x4 on PCB, x8 Not Required
x8, x4	x8	x4	Controller 1 [0:7]								–				Controller 0 [3:0]¹				Quad 104, REFCLK 0	Quad 102, REFCLK 0	x4, x4	x8 Not Required, x4 on PCB
A x1 link width uses lane 0 of the x4 configuration. A x2 link width uses lanes 1:0 of the x4 configuration. This should be reversed on the PCB.

Note: For devices with CPM5, the Vivado pinout report shows CPM5 lanes in reverse order for x16 and x8 links; use the information in this product guide as a reference instead of the Vivado pinout report.

Board designs for x2 and x1 must use x4 guidance. For x2 board designs, based on the controller to be used, connect to controller lane numbers Controller 0 [1:0] or Controller 1 [1:0]. Similarly, for x1 board designs, connect to controller lane numbers Controller 0 [0] or Controller 1 [0]. Note that controller lane numbers might not be the same as physical GTYP channel numbers in a quad. Consult the provided placement table.