AXI Bridge Slave ports are connected from the AMD Versal device Network on Chip (NoC) to the CPM DMA internally. For Slave Bridge AXI4 details, see the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).
To access QDMA registers, you must follow the protocols outlined in the AXI Slave Bridge Register Limitations section.