AXI Memory Mapped Writeback Status Structure for H2C and C2H - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)
Document ID
PG347
Release Date
2025-05-29
Version
3.4 English

The MM writeback status register is located after the last entry of the (H2C or C2H) descriptor.

Table 1. AXI Memory Mapped Writeback Status Structure for H2C and C2H
Bit Bit Width Field Name Description
[63:48] 16 reserved Reserved
[47:32] 16 pidx Producer Index at time of writeback
[31:16] 16 cidx Consumer Index
[15:2] 14 reserved Reserved
[1:0] 2 err

Error

bit 1: Descriptor fetch error

bit 0: DMA error