AXI Bridge for PCIe Interrupts - AXI Bridge for PCIe Interrupts - 3.4 English

AXI Bridge for PCIe Interrupts - AXI Bridge for PCIe Interrupts - 3.4 English - PG347

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document_ID

PG347

Release_Date

2026-07-31

Version

3.4 English

Table 1. AXI Bridge for PCIe Interrupts
Signal Name	I/O	Description
bridge0_usr_irq_in	I	User interrupt request. Asset to generate an interrupt and maintain assertion until interrupt is serviced.
bridge0_usr_irq_ack[NUM_USR_IRQ-1:0]	O	User interrupt acknowledge. Indicates that the interrupt has been set on PCIe. Two acks are generated for legacy interrupt. One ack is generated for MSI/MSI-X interrupts.

NUM_USR_IRQ is selectable and it ranges from 0 to 15. Each bits in bridge0_usr_irq_req bus corresponds to the same bits in bridge0_usr_irq_ack. For example, bridge0_usr_irq_ack[0] represents an ack for bridge0_usr_irq_req[0].