Versal_CPM5_Two_Port_Switch_Design - 3.4 English - PG346

• This design has the following two preset options:
  • CPM5 PCIe Controller 0 enabled in Gen5x4 configuration as an Upstream Port, connected via Switch Logic to a PL PCIE5 Controller 0 enabled in Gen5x4 configuration as a Downstream Port.
  • CPM5 PCIe Controller 0 enabled in Gen5x4 configuration as a Downstream Port, connected via Switch Logic to a PL PCIE5 Controller 0 enabled in Gen5x4 configuration as an Upstream Port.
• This design targets xcvp1202-vsva2785-2MHP-e-S part, and supports simulation, synthesis, and implementation flows.
• This design demonstrates the use of the Upstream Port and Downstream Port modes in CPM5.