Straddle Option for RC Interface - Straddle Option for RC Interface - 3.4 English - PG346

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)
Document ID
PG346
Release Date
2025-12-03
Version
3.4 English

The RC interface of the PCIe® core has the capability to start up to eight Completions in the same beat on the requester completion interface. This straddle option is enabled during core customization in the AMD Vivado™ IDE. The straddle option can be used only with the Dword-aligned mode.

When the straddle option is enabled, Completion TLPs are transferred on the AXI4-Stream interface as a continuous stream, with no packet boundaries. Thus, the signals m_axis_rc_tkeep and m_axis_rc_tlast are not useful in determining the boundaries of Completion TLPs delivered on the interface (the core sets m_axis_rc_tkeep to all 1s and m_axis_rc_tlast to 0 permanently when the straddle option is in use.). Instead, delineation of TLPs is performed using the following signals provided within the m_axis_rc_tuser bus.

  • is_sop[7:0]: The core sets this output to a non-zero value in a beat when there is at least one Completion TLP starting in the beat. When straddle is disabled, only is_sop[0] is valid and is_sop[7:1] are permanently set to 0. When straddle is enabled, the settings are as follows:
    • 00000000: No new TLP starting in this beat.
    • 00000001: A single new TLP starts in this beat. ts start position is indicated by is_sop0_ptr[1:0].
    • 00000011: Two new TLPs are starting in this beat. is_sop0_ptr[1:0] provides the start position of the first TLP and is_sop1_ptr[1:0] provides the start position of the second TLP.
    • 00000111: Three new TLPs are starting in this beat. is_sop0_ptr[1:0] provides the start position of the first TLP, is_sop1_ptr[1:0] provides the start position of the second TLP, and is_sop2_ptr[1:0] provides the start position of the third TLP.
    • 00001111: Four new TLPs are starting in this beat. is_sop0_ptr[1:0] provides the start position of the first TLP, is_sop1_ptr[1:0] provides the start position of the second TLP, is_sop2_ptr[1:0] provides the start position of the third TLP, and is_sop3_ptr[1:0] provides the start position of the fourth TLP.
    • 00011111: Five TLPs starting in this beat, at locations determined by is_sop0_ptr[2:0], is_sop1_ptr[2:0], is_sop2_ptr[2:0], is_sop3_ptr[2:0] and is_sop4_ptr[2:0], respectively.
    • 00111111: Six TLPs starting in this beat, at locations determined by is_sop0_ptr[2:0], is_sop1_ptr[2:0], is_sop2_ptr[2:0], is_sop3_ptr[2:0], is_sop4_ptr[2:0] and is_sop5_ptr[2:0], respectively.
    • 01111111: Seven TLPs starting in this beat, at locations determined by is_sop0_ptr[2:0], is_sop1_ptr[2:0], is_sop2_ptr[2:0], is_sop3_ptr[2:0], is_sop4_ptr[2:0], is_sop5_ptr[2:0] and is_sop6_ptr[2:0], respectively.
    • 11111111: Eight TLPs starting in this beat, at locations determined by is_sop0_ptr[2:0], is_sop1_ptr[2:0], is_sop2_ptr[2:0], is_sop3_ptr[2:0], is_sop4_ptr[2:0], is_sop5_ptr[2:0], is_sop6_ptr[2:0], and is_sop7_ptr[2:0] respectively.
    • All other settings are reserved.
  • is_sop0_ptr[2:0]: When is_sop[0] is set, this field indicates the offset of the first Completion TLP starting in the current beat. Valid settings are as follows:
    • 000 - TLP starting at Byte lane 0
    • 001 - Byte lane 16
    • 010 - Byte lane 32
    • 011 - Byte lane 48
    • 100 - Byte lane 64
    • 101 - Byte lane 80
    • 110 - Byte lane 96
    • 111 - Byte lane 112
  • is_sop1_ptr[7:0]: When is_sop[1] is set, this field indicates the offset of the second Completion TLP starting in the current beat. Valid settings is equivalent to is_sop0_ptr[7:0] except value 'h0 is not valid.
  • is_eop[7:0]: These outputs signals that one or more TLPs are ending in this beat. These outputs are set in the final beat of a TLP. When straddle is disabled, only is_eop[0] is valid and is_eop[7:1] are permanently set to 0. When straddle is enabled, the settings are as follows:
    • 00000000: No TLPs ending in this beat.
    • 00000001: A single TLP is ending in this beat. is_eop0_ptr[3:0] provides the offset of the last Dword of this TLP.
    • 00000011: Two TLPs are ending in this beat. is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP and is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP.
    • 00000111: Three TLPs are ending in this beat. is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP, is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP, and is_eop2_ptr[3:0] provides the offset of the last Dword of the third TLP.
    • 00001111: Four TLPs are ending in this beat. is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP, is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP, is_eop2_ptr[3:0] provides the offset of the last Dword of the third TLP, and is_eop3_ptr[3:0] provides the offset of the last Dword of the fourth TLP.
    • 00011111: Five TLPs ending in this beat, at locations determined by is_eop0_ptr[4:0], is_eop1_ptr[4:0], is_eop2_ptr[4:0], is_eop3_ptr[4:0] and is_eop4_ptr[4:0], respectively.
    • 00111111: Six TLPs ending in this beat, at locations determined by is_eop0_ptr[4:0], is_eop1_ptr[4:0], is_eop2_ptr[4:0], is_eop3_ptr[4:0], is_eop4_ptr[4:0] and is_eop5_ptr[4:0], respectively.
    • 01111111: Seven TLPs ending in this beat, at locations determined by is_eop0_ptr[4:0], is_eop1_ptr[4:0], is_eop2_ptr[4:0], is_eop3_ptr[4:0], is_eop4_ptr[4:0], is_eop5_ptr[4:0] and is_eop6_ptr[4:0], respectively.
    • 11111111: Eight TLPs ending in this beat, at locations determined by is_eop0_ptr[4:0], is_eop1_ptr[4:0], is_eop2_ptr[4:0], is_eop3_ptr[4:0], is_eop4_ptr[4:0], is_eop5_ptr[4:0], is_eop6_ptr[4:0] and is_eop7_ptr[4:0], respectively.
    • All other settings are reserved.
  • is_eop0_ptr[4:0]: When is_eop[0] is set, this field provides the offset of the last Dword of the first TLP ending in this beat. The offset for the last byte can be determined from the starting address and length of the TLP, or from the byte enable signals byte_en[63:0].
  • is_eop1_ptr[7:0]: When is_eop[1] is set, this field provides the offset of the last Dword of the second TLP ending in this beat.
Note: Only two sets of sop, eop, and ptrs are described. Refer to the port list for the remaining ports.

The following figure illustrates the transfer of 11 Completion TLPs on the requester completion interface when the straddle option is enabled. The first Completion TLP (COMPL 1) starts at Dword position 0 of Beat 1 and ends in Dword position 2 of Beat 2. The second TLP (COMPL 2) starts in Dword position 8 of the same beat and ends in Dword position 14. Thus, there is one TLP starting in Beat 1, whose starting position is indicated by is_sop0_ptr, and two TLPs ending, whose ending Dword positions are indicated by is_eop0_ptr and is_eop1_ptr, respectively.

Beat 3 has COMPL 3 starting at Dword offset 8, ending at Dword offset10. There is also a second TLP (CMPL 4) in the same beat, starting at Dword offset 12 and continuing to the next beat. In this beat, is_sop0_ptr points to the starting Dword offset of COMPL 3 and is_sop1_ptr points to the starting Dword offset of COMPL 4. is_eop0_ptr points to the offset of the last Dword offset of COMPL 4.

Beat 4 has COMPL 4 ending with Dword offset 0, and has three new complete TLPs in it (COMPL 5, 6 and 7). The starting Dword offsets of the new Completions 5, 6 and 7 are provided by is_sop0_ptr, is_sop1_ptr, and is_sop2_ptr, respectively. The ending offsets of Completions 4, 5, 6 and 7 are indicated by is_eop0_ptr, is_eop1_ptr, is_eop2_ptr and is_eop3_ptr, respectively.

Finally, Beat 5 contains four complete TLPs (COMPL 8 – 11). Their starting Dword offsets are signaled by is_sop0_ptr, is_sop1_ptr, is_sop2_ptr and is_sop3_ptr, respectively. The ending offsets are indicated by is_eop0_ptr, is_eop1_ptr, is_eop2_ptr and is_eop3_ptr, respectively. Thus, all the four SOP and EOP pointers provide valid information in this beat.

Figure 1. Transfer of Completion TLPs on the Requester Completion Interface with the Straddle Option Enabled