Segmented Configuration - 3.4 English - PG346

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-11-22
Version
3.4 English

Segmented Configuration is a solution that enables designers to boot the processors in a Versal device and access DDR memory before the programmable logic (PL) is configured. This allows DDR-based software like Linux to boot first followed by the PL, which can be configured later if needed via any primary or secondary boot device or through a DDR image store. The Segmented configuration feature is intended to present the Versal boot sequence with similar flexibility to configure PL as can be done with AMD Zynq™ UltraScale+™ MPSoCs.

This solution uses a standard Vivado tool flow through implementation, with the only additional annotation required is the identification of NoC path segments to be included in the initial boot image. This occurs automatically after the project property enabling the feature is set. Programming image generation (write_device_image) automatically splits the programming images into two PDI files to be stored and delivered separately. The entire PL is dynamic and it can be completely reloaded while any operating system and DDR memory access remain active.

Segmentation of Versal adaptive SoC programming images allow the processing domain, which includes the CPM to be available much more quickly than with a monolithic programming solution. The difference between Tandem Configuration and Segmented Configuration is where the split is done. Tandem includes only the necessary elements for link training in stage 1 – CPM, GTY, and PMC. Segmented includes everything except the programmable logic (PL) domain along with NoC resources within that domain.

Additional tuning of the boot PDI is done to combine the Tandem approach with Segmented Configuration to ensure the 120 ms link training goal is met, but only for specific Versal Premium and HBM devices in this release. When Segmented Configuration is enabled for a design with one or both CPM5 controllers set to end point mode, the resulting boot PDI is structured as a Tandem image. You can deliver the PLD PDI over the PCIe link using QDMA or any other available interface. The equivalent support for CPM4 devices is planned for a future release.

Table 1. Segmented Configuration Feature
Feature CPM4 Devices CPM5 Devices
Tandem Configuration Available (Tandem PROM or Tandem PCIe) Available (Tandem PROM or Tandem PCIe)
120 ms enumeration with Tandem Configuration Yes Yes
Segmented Configuration Available Available
120 ms enumeration with Segmented Configuration No Yes
Note: In the Vivado 2024.2 release, select one feature or the other. Selecting both Tandem and Segmented options results in an error during write_device_image.

To load PLD (Segmented) or partial (DFX) PDI images over the CPM QDMA interface, PCIe must be declared as a secondary boot interface. In the boot.bif generated by the Vivado flow (found in the implementation runs directory), add a single line. Insert boot_device { pcie } after line 5 (id = 0x2). This is automatically managed when Tandem PCIe is selected, but must be declared when using Segmented Configuration or DFX.

Figure 1. boot.bif

For more information on Segmented Configuration, including design requirements and a tutorial walk-through, see the Segmented Configuration tutorial available on the AMD Vivado GitHub repository.