Preparing the Test Bench - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English
  • You might choose to use the PCIe example designs from earlier generation (UltraScale+) or Soft IP variant of the DUT. CPM5 QDMA is compatible with QDMA Soft IP v4.0. CPM4 QDMA is compatible with QDMA Soft IP v3.0. BMD and XDMA variants are compatible with any version.
    Note: AMD PCIe simulation test bench often has hierarchical references and/or register offset/value differences, which need to be adapted to the new design.
  • Instantiate both the DUT and the complement PCIe and connect the GT serial lines and provide PCIe reference clock.
    Note: Do not provide PCIe reset as it is provided in the next step via APIs.
  • If your design has NOC, you must use <top level module name>_sim_wrapper instantiation. For example, if your top level module called design_1_wrapper, you must instantiate design_1_wrapper_sim_wrapper in your test bench. This file is not be visible in your Vivado project file hierarchy until simulation is launched (or simulation script is generated) from Vivado tool.

    This file is required to be used as it contains XLNOC model required to route packets through NOC.

  • Add all required PS9 Clock, Reset, and Routing Init APIs into your design (you might copy from the provided board.v file in the package) or see the next page for examples. This is required to generate clock, reset, and routing internal to the CPM and PS9. Description of each API is provided in sections.
  • Add QDMA register programming (you might copy from the provided usp_pci_exp_usrapp_tx.v file in the package) into your test bench. These are registers that would be programmed by drivers, such as Host Profile programming (CPM5 QDMA only), Queue Contexts.

board.v addition - PS9 Init APIs

// RP cdo file
  defparam board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.cpm_0.inst.CPM_INST.SIM_CPM_CDO_FILE_NAME = "rp_cpm_data_sim.cdo";
  
  parameter ON=3, OFF=4, UNIQUE=32, UNIQUE0=64, PRIORITY=128;
  reg lpdcpmtopswclk;
  
  initial begin
    // Create clocks for the CPM LPD domain to NOC clock (lpdcpmtopswclk)
    // Set the frequency based on GUI selection.
    lpdcpmtopswclk = 0;
    forever #(500) lpdcpmtopswclk = ~lpdcpmtopswclk;
  end

initial begin
  // Create the PS-VIP clock
  force board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.versal_cips_ps_vip_clk = lpdcpmtopswclk;
  force board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.versal_cips_ps_vip_clk = lpdcpmtopswclk;
   
  // Set VIP PL output clocks based on GUI selection
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(0,250);
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(1,250);
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(2,250);
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(3,250);
   
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(0,250);
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(1,250);
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(2,250);
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_clock(3,250);
   
  // Generate Reference Clocks for the CPM
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.cpm_gen_clock(33.33); // This was 100MHz, but it should be 33.33MHz.
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.cpm_osc_clk_div2_gen_clock(200); // Sim Speedup, you can set to 500-1GHz (>200 is not HW supported)
 
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.cpm_gen_clock(33.33); // This was 100MHz, but it should be 33.33Mhz.
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.cpm_osc_clk_div2_gen_clock(200); // Sim Speedup, you can set to 500-1GHz (>200 is not HW supported)
   
  // Enable CPM PS AXI to PS NOC AXI routing (both AXI MM 0 and AXI MM 1)
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.set_routing_config("CPMPSAXI0","PSNOCPCIAXI0",1);
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.set_routing_config("CPMPSAXI1","PSNOCPCIAXI1",1);
   
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.set_routing_config("CPMPSAXI0","PSNOCPCIAXI0",1);
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.set_routing_config("CPMPSAXI1","PSNOCPCIAXI1",1);
   
  // Assert PCIe reset
  $display("[%t] : System Reset Is Asserted...", $realtime);
  // Root Port reset assert
  sys_rst_n = 1'b0;
  // Endpoint reset assert based on GUI selection for each controller
  force board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST0N = 1'b0;
  force board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST1N = 1'b0;
  // Assert VIP PL output resets based on GUI Selection
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_reset(4'h0);
  // POR reset is the master reset for the PS Simulation Model. Deserting will enable the PS-VIP.
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.por_reset(0);
   
  // RP reset assert based on GUI selection for each controller
  force board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST0N = 1'b0;
  force board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.PERST1N = 1'b0;
  // Assert VIP PL output resets based on GUI Selection
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_reset(4'h0);
  // POR reset is the master reset for the PS Simulation Model. Deserting will enable the PS-VIP.
  board.RP.design_rp_wrapper_i.design_rp_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.por_reset(0);
 
  // Release resets after some delay
  repeat (500) @(posedge rp_sys_clk_p);
  $display("[%t] : System Reset Is De-asserted...", $realtime);
  // Root port reset release
  sys_rst_n = 1'b1;
  // De-Assert VIP PL output resets based on GUI Selection
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.pl_gen_reset(4'hF);
  // Release reset on the PS-VIP
  board.EP.design_1_wrapper_i.design_1_i.versal_cips_0.inst.pspmc_0.inst.PS9_VIP_inst.inst.por_reset(1);