MCAP Status Register (0x08, RW) - 3.4 English - PG346

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-11-22
Version
3.4 English

The MCAP Status Register is used to view the status of the MCAP during operations. The following table describes the fields within the MCAP Status Register.

Bit Location Description Initial Value
3:0 Reserved N/A
5:4 Read/Write Status: Reflects the status of AXI read or write transactions issued to the Versal NOC by the MCAP Extended Capability. This bit is cleared by asserting the MCAP Reset bit in the MCAP Control Register.
  • 0b00: OK
  • 0b01: SLVERR
  • 0b10: DECERR
  • 0b11: Reserved
00
7:6 Reserved N/A
8 Read/Write Complete: Indicates that the MCAP read has completed and that data is available in the MCAP Read Data Register (0x1C). This bit is cleared by asserting the MCAP Reset bit in the MCAP Control Register.

When switching from generating AXI reads to AXI writes the Read Complete bit must be checked and asserted for the last Read operation. This is to ensure there are no outstanding transactions in the MCAP and NOC pipeline before switching to generate AXI write transactions.

0
15:9 Reserved N/A
20:16 FIFO Occupancy: Indicates the FIFO Occupancy level. The Versal MCAP Extended Capability FIFO has X entries. 0x00
21 Write FIFO Full: Indicates that the MCAP internal FIFO is Full. Under normal operation this condition should never be met because the FIFO should drain faster than the host can fill the FIFO. 0
22 Write FIFO Almost Full: Indicates that the MCAP FIFO fill level is almost full. This represents XX of the XX FIFO capacity. 0
23 Write FIFO Almost Empty: Indicates that the MCAP FIFO fill level is almost empty. This represents XX of the XX FIFO capacity. 1
24 Write FIFO Empty: Indicates that the MCAP FIFO is empty.

The MCAP FIFO must be empty before switching from generating AXI writes to generating AXI read transactions. This is to enure all of the transactions in the MCAP FIFO have been processed and issued to the NOC prior to switching to generated AXI read transactions to the NOC. Similarly the MCAP FIFO must also be empty before enabling or disabling 16 byte (128-bit) transactions. This will ensure that all data in the pipeline has been flushed and that there are no partial transactions retained in the FIFO.

1
25 Write FIFO Overflow: Indicates that the MCAP FIFO has overflowed. This means data has been lost and not all data will be received by the target. Under normal operation this condition should never happen. If this bit is set SW should report an appropriate error message to the user. 0
31-26 Reserved N/A