MCAP Control Register (0x0C, RW) - 3.4 English - PG346

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-11-22
Version
3.4 English

The use of MCAP Control and MCAP Status registers can be used to perform MCAP read and write operations. The following table describes the fields within the MCAP Control Register.

Bit Location Description Initial Value
0 MCAP Read Enable: When this bit is asserted read transactions will be issued to the NOC when the MCAP Read/Write Address Register (0x14) is updated. All read transactions issued to the NOC will be 32-bit read transactions.

This field should only be enabled when the MCAP FIFO is empty. This ensures all transactions in the MCAP FIFO have been processed prior to enabling the generation of NOC read transactions.

This field should only be disabled when the read complete bit has been asserted for the last read issued through the MCAP interface. This ensures all transactions in the MCAP FIFO have been processed and that all responses have been received from the NOC.

0x1
3:1 Reserved N/A
4 MCAP Write Enable: When this bit is asserted write transactions are issued.

This field should only be enabled or disabled when the MCAP FIFO is empty. This ensures that all the transactions in the MCAP FIFO have been processed prior to enabling or disabling the generation of NOC write transactions.

0
5 MCAP 128-bit Mode: When this bit is asserted the MCAP issues 128-bit (16 byte) transactions to the NOC rather than 32-bit transactions to the NOC. This is needed to access specific slaves within the Versal device that require 128-bit data transactions.

The PMC Salve Boot Interface (SBI) is used to program Tandem Stage2 or Dynamic Function Exchange (DFX) .pdi files. Transactions to this interface must be 128 bytes minimum. When writing to the PMC SBI the 128-bit mode must be used.

0
7:6 Reserved N/A
8 MCAP Reset: This bit is used to reset the MCAP interface and registers. 0
15:9 Reserved N/A
19:16 AXI Cache: This field sets how the AXI transactions to the NOC will drive the AXICACHE[3:0] bits for each of the generated AXI transactions. 0x0
22:20 AXI Protect: This field sets how the AXI transactions to the NOC will drive the AXIPROT[2:0] bits for each of the generated AXI transactions. 0x0
31:23 Reserved N/A