The CPM5 block contains two high-performance PCI Express ports that are independently customizable. Designs can interface with programmable logic and clocking resources using fabric interconnect.
All feature references are applicable to both PCI Express ports in the CPM5 block, with the following exception:
- PCIe Port 0 supports up to x16 operation
- PCIe Port 1 supports up to x8 operation
Features of the CPM5 block are listed below:
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PCI Express Architecture Components Supported include:
- PCI Express Endpoint, Legacy Endpoint
- Root Port
- Switch Upstream and Downstream Ports
- x1, x2, x4, x8, or x16 link widths
- Gen1, Gen2, Gen3, Gen4, or Gen5 link speeds (Gen5 support limited to x8)
- CCIX supported in PCI Express and EDR PHY Modes.
- PCI Express Support: Gen4x4, Gen4x8, Gen4x16, Gen5x4, and Gen5x8
- EDR Support: x4 and x8 link width capability
-
AXI4-Stream Interfaces to Programmable Logic (PL)
- Configurable 64-bit/128-bit/256-bit/512-bit/1024-bit interface data path widths (newly added 1024 bit support)
- Configurable 62.5 MHz/125 MHz/250 MHz interface data path speeds
- Four Independent Initiator/Target, Request/Completion AXI4-Stream
- Parity protection on internal logic data paths and external data path interfaces
- Advanced Error Reporting (AER) and End-to-End CRC (ECRC)
- Two PCI Express Virtual Channels:
- One PCI Express Compliant Virtual Channel, eight Traffic Classes
- One CCIX Compliant Virtual Channel
- Supports multiple Functions and Single-Root IO Virtualization
- Up to 16 Physical Functions
- Up to 4080 Virtual Functions
- PASID Prefix Capability Supported.
- Built-in lane reversal and receiver lane-lane de-skew
- 3 x 64-bit or 6 x 32-bit Base Address Registers (BARs) that are
fully configurable
- Expansion ROM BAR supported
- All Interrupt types are supported
- INTx
- 32 multi-vector MSI capability
- MSI-X capability with up to 32k vectors with built-in MSI-X vector tables
- Built-in Initiator Read Request/Completion Tag Manager
- Configurable 256 (Extended Tag); OR
- Up to 768 (Scaled Tag) outstanding Initiator Read Request Transactions supported
- CCIX Configuration Capabilities
- Transport and Protocol DVSECs
- Features that enable high performance applications
- AXI4-Stream TLP Straddle on Requester Completion Interface
- Up to 1024 RX Completion Header Credits and 64 KB RX Completion Payload Space
- Relaxed Transaction Ordering in the Receive Data Path
- Address Translation Services (ATS) and Page Request Interface (PRI) Messaging
- Atomic Operation Transactions Support
- Transaction Tag Scaling as Completer
- Flow Control Scaling
- PCI Express Component Measurement and Authentication (CMA) capability
- Several ease of use and configurable features are supported:
- BAR and ID based filtering of received transactions
- Optional ASPM support for endpoint port types only; ASPM is not supported for other port types.
- Configuration extend interface
- AXI4-Stream interfaces address align mode
- Debug and diagnostics interface