Completer Completion Interface - Completer Completion Interface - 3.4 English - PG346

Completion data from the user application to the core. Only the lower 128 bits are used when the interface width is 128 bits, and only the lower 64 bits are used when the interface width is 64 bits.

This set of signals contain sideband information for the TLP being transferred. These signals are valid when pcie(n)_s_axis_cc_tvalid is High.

Table 2 describes the individual signals in this set.

The user application must assert this signal in the last cycle of a packet to indicate the end of the packet. When the TLP is transferred in a single beat, the user application must set this bit in the first cycle of the transfer.

The assertion of bit i of this bus during a transfer indicates to the core that Dword i of the pcie(n)_s_axis_cc_tdata bus contains valid data. Set this bit to 1 contiguously for all Dwords starting from the first Dword of the descriptor to the last Dword of the payload. Thus, pcie(n)_s_axis_cc_tkeep must be set to all 1s in all beats of a packet, except in the final beat when the total size of the packet is not a multiple of the width of the data bus (both in Dwords). This is true for both Dword-aligned and address-aligned modes of payload transfer.

Bits [7:4] of this bus are not used by the core when the interface width is configured as 128 bits, and bits [7:2] are not used when the interface width is configured as 64 bits.

The user application must assert this output whenever it is driving valid data on the pcie(n)_s_axis_cc_tdata bus. The user application must keep the valid signal asserted during the transfer of a packet. The core paces the data transfer using the pcie(n)_s_axis_cc_tready signal.

Activation of this signal by the core indicates that it is ready to accept data. Data is transferred across the interface when both pcie(n)_s_axis_cc_tvalid and pcie(n)_s_axis_cc_tready are asserted in the same cycle.

If the core deasserts the ready signal when the valid signal is High, the user application must maintain the data on the bus and keep the valid signal asserted until the core has asserted the ready signal.

The user application can assert this signal during any cycle during the transfer. It can either choose to terminate the packet prematurely in the cycle where the error was signaled, or can continue until all bytes of the payload are delivered to the core. In the latter case, the core treats the error as sticky for the following beats of the packet, even if the user application deasserts the discontinue signal before the end of the packet.

The discontinue signal can be asserted only when pcie(n)_s_axis_cc_tvalid is High. The core samples this signal only when pcie(n)_s_axis_cc_tready is High. Thus, when asserted, it should not be deasserted until pcie(n)_s_axis_cc_tready is High.

When the core is configured as an Endpoint, this error is also reported by the core to the Root Complex to which it is attached, using AER.

When parity checking is enabled in the core, user logic must set bit i of this bus to the odd parity computed for byte i of pcie(n)_s_axis_cc_tdata. Only the lower 16 bits are used when the interface width is 128 bits, and only the lower 8 bits are used when the interface width is 64 bits.

When an interface parity error is detected, it is recorded as an uncorrectable internal error and the packet is discarded. According to the Base Spec 6.2.9, an uncorrectable internal error is an error that occurs within a component that results in improper operation of the component. The only method of recovering from an uncorrectable internal error is a reset or hardware replacement.

The parity bits can be permanently tied to 0 if parity check is not enabled in the core.