The following features are not supported in the core:
- Powering down of lane 0 (master) is not supported.
- Per-lane power down is not supported.
- PIPE low power state of P0s is not supported when the max speed is configured as Gen3 or Gen4.
- PIPE low power state of P2 is not supported.
- Bypassing the RX elastic buffer is not supported.
- Preserving of Gen3/Gen4 equalization settings is not supported after the rate change.
- PCIe PHY does not check or monitor for PIPE protocol errors.
- Checking or monitoring for PIPE protocol errors is not supported.
- Tandem Configuration is not available or applicable for this core. For 100 ms enumeration of PCIe end points, the CPM mode for PCI Express must be used; for more information, see Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346). PL-based PCIe cores, as described in Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343), does not support Tandem Configuration at this point.
- This IP architecture assumes exclusive use of one or more complete GT quads, regardless of the designed link width. While it might be possible to share unused lanes in the GT quad with other instances of this IP, non-PCIe IPs, or custom GT-based interfaces for x2 and x1 link widths, AMD does not support evaluations or implementations of such sharing arrangements. The feasibility of sharing depends on the specific GT configuration required for other protocols, links, and lanes intended to share the GT quad. Factors affecting GT configuration include external REFCLKs, fabric design clocks and resets, GT clock management resources, connectivity rules, mode, and electrical settings.