TX Equalization Signals for Gen3 and Above Rate (for AMD MAC) - 1.0 English

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)

Document ID
PG345
Release Date
2024-06-05
Version
1.0 English
Table 1. TX Equalization Signals for Gen3 and Above Rate (for AMD MAC)
Name Width Direction Clock Domain Description
phy_txprecursor 5 input pclk Transmitter pre-cursor TX pre-emphasis control. Link Equalization settings. Per-Lane.
phy_txmaincursor 7 input pclk Transmitter post-cursor TX pre-emphasis control. Link Equalization settings. Per-Lane.
phy_txpostcursor 5 input pclk Transmitter main-cursor coefficients. Link Equalization settings. Per-Lane.