The AMD Versal™ Adaptive SoC PHY for PCIe® IP is a building block IP that allows for a PCI Express® MAC to be built as soft IP in the device fabric. The Versal adaptive SoC PCIe PHY IP design cannot be migrated to AMD UltraScale™ or AMD UltraScale+™ parts.
Note: IP supports
AMD Vivado™
IP integrator flow. The GT Quads are always
outside the PHY for PCIe IP and connected in IP integrator block design.
Important: In this product guide, AMD UltraScale+™
refers to both the
existing UltraScale+ and the new Spartan UltraScale+ devices.