Generating Example Design - 1.1 English - PG345

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)
Document ID
PG345
Release Date
2025-05-29
Version
1.1 English

For generating the IP Core, see Designing with the Core.

Figure 1. Adding Versal Adaptive SoC PHY for PCI Express Core into IPI Design

Figure 2. Configuring pcie_phy_versal IP

After the IP is generated, right-click the IP to generate the example design as shown in subsequent figures:

Figure 3. Open IP Example Design

Figure 4. Example Design for Gen5x4

Figure 5. Example Design for Gen3x16

Following is the example design operation:

  • The example design expects the system reset to be received from the link partner.
  • You have an additional option to override the system reset using sys_rst_override provided in the example design. This can be connected to any I/O on the board, such as a switch pin.
  • The TX and RX electrical idle is high at this point.
  • The design waits for the reset sequence to finish. For more information on the reset sequence, see Resets.
  • The transceiver provides the phystatus_rst which indicates that the PHY is ready. Make sure the PCIe MAC is connected to this output from the PHY.
  • The design now waits for phystatus on all lanes.
  • Based on your selection of phyrate (either Gen1, Gen2, Gen3, Gen4 or Gen5), the design changes to the desired speed.