This section provides a detailed description of the features, attributes, and signals associated with the PIPE interfaces of the Versal™ Adaptive SoC PHY for PCIe® IP. The following figure is a high-level PCIe PHY IP block diagram:
Figure 1. PCIe PHY IP Block Diagram
- Lane 0 is always the master.
- Clock block shared by all lanes.
- The Versal adaptive SoC PHY IP communicates with the PCIe MAC through the PIPE interface.