Clocking - 1.1 English - PG345

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)
Document ID
PG345
Release Date
2025-05-29
Version
1.1 English
  • The AMD Versal™ Adaptive SoC PHY for PCI Express® IP GTY can be configured to support PCIe® applications with 100 MHz, 125 MHz, or 250 MHz reference clock.
  • The reference clock can be synchronous or asynchronous.
  • The phy_pclk is the primary clock for the PIPE interface, FPGA fabric, and GTY [TX/ RX] usrclk and [TX/RX] usrclk2.
  • In addition to phy_pclk, there are other clocks (phy_coreclk, phy_userclk2, phy_userclk) available to support the PCIe MAC.
  • BUFG_GTs are used to generate these clocks, so MMCM is not required.
  • To use the reference clock for FPGA fabric, another BUFG_GT must be used.
  • The source of the GTY reference clock must come directly from IBUFDS_GTE5.

The following figure shows clocking architecture for the Versal adaptive SoC PCIe PHY IP configured for x2 lane width.

Figure 1. Clock Architecture
PIPE_CLK (phy_pclk)
Provided to Versal device GTY to clock the PIPE interface. PIPE Clock must be 125 MHz for Gen1 operation or 250 MHz for Gen2/Gen3 and 500 MHz for Gen4/Gen5 operation. Note that the PIPE interface data width is 16 bits for Gen1 or Gen2 operation, 32 bits for Gen3, and Gen4 operation, 64 bits for Gen5. PIPE Clock frequency input to the block is switched dynamically based on the current selected speed of operation is accomplished using a BUFG_GT resource from the FPGA global clocking infrastructure.
CORE_CLK (phy_coreclk)
CORE_CLK is the dominant clock domain in the PCIe block, core_clk is also used to drive UltraRAMs interfaced with the Hard Block.
USER_CLK (phy_userclk)
Clocks the non- AXI4 ST user interfaces. The frequency can be 62.5, 125, 250 or 500 MHz, depending on the data rate, number of lanes and Transaction Interface width.
USER_CLK2 (phy_userclk2)
Clocks the AXI4 ST user interfaces. External to the block user_clk2 is the same as (and driven by the same BUFG_GT) either core_clk or user_clk depending on the configuration. Internal to the block user_clk2 is created using core_clk and user_clk_en and similarly matches either core_clk or user_clk.

PIPE_CLK, CORE_CLK, USER_CLK, and USER_CLK2 are derived from the same TXOUTCLK provided by the AMD Versal™ GTY Quad instance. Each of these clocks are driven by a separate BUFG_GT instance which produces different clock frequencies while minimizing clock skew between them.