Clock and Rest Signals Interface Ports - Clock and Rest Signals Interface Ports - 1.1 English - PG345

Versal Adaptive SoC PHY for PCI Express LogiCORE IP Product Guide (PG345)
Document ID
PG345
Release Date
2025-05-29
Version
1.1 English
Table 1. Clock and Reset Signals
Port Name Width I/O Clock Description
phy_refclk 1 Input refclk Reference clock for fabric logic. The recommended reference clock is 100 MHz. This clock is expected to be free running and stable. This reference clock can be either synchronous or asynchronous. In synchronous mode, the PPM is 0. In asynchronous mode, the PPM is up to ±300 or 600 PPM worst case.The on-board differential reference clock must drive a IBUFDSGTE instance. This IBUFDSGTE has two output pins, the IBUF_DS_ODIV2 output pin via a BUFG_GT buffer should be used to generate the phy_refclk.
  • 100 MHz (default)
  • 125 MHz
  • 250 MHz
phy_gtrefclk 1 Input refclk Reference clock for GT_QUADS. The frequency and PPM requirement is same as phy_refclk. This is derived from same IBUFDSGTE instance, which is used to generate the phy_refclk. This clock must be driven directly from IBUFDSGTE instance's IBUF_OUT pin.
sys_reset 1 Input Asynchronous When logic Low, this signal resets the PHY. This must be connected to PCIe PERST_N. Polarity is Active Low.
phy_coreclk 1 Output coreclk Core clock options:
  • 250 MHz
  • 500 MHz
phy_userclk 1 Output userclk User clock options:
  • 62.5 MHz
  • 125 MHz
  • 250 MHz
  • 500 MHz
phy_userclk2 1 Output userclk This clock is same as phy_coreclk or phy_userclk depending on the configuration. No user option is added at present. Not recommended to use.
phy_mcapclk 1 Output mcapclk This clock is same as phy_userclk. No user option is added at present. Not recommended to use.
phy_pclk 1 Output pclk Not configurable by user. Operations frequencies are:
  • 125 MHz: Gen1 operating speed
  • 250 MHz: Gen2 and Gen3 operating speed
  • 500 MHz: Gen4 and Gen5 operating speed