SGDMA Descriptor Control Register (0x18) - SGDMA Descriptor Control Register (0x18) - 2.0 English

SGDMA Descriptor Control Register (0x18) - SGDMA Descriptor Control Register (0x18) - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document_ID

PG344

Release_Date

2026-07-22

Version

2.0 English

Table 1. SGDMA Descriptor Control Register (0x18)
Bit Index	Default	Access Type	Description
		W1C	Bit descriptions are the same as in SGDMA Descriptor Control Register (0x10).