The following table describes the possible scenarios and outcomes:
| MSIX Enable (MSIX capability) | MSIX Mask (MSIX capability) | Mask Per Vector (in MSIX table) | usr_irq_ack/Fail Outcome | Interrupt at Host |
|---|---|---|---|---|
| 0 | 0 | 0 | usr_irq_fail asserted | Not Received |
| 0 | 0 | 1 | usr_irq_fail | Not Received |
| 0 | 1 | 0 | usr_irq_fail | Not Received |
| 0 | 1 | 1 | usr_irq_fail | Not Received |
| 1 | 0 | 0 | usr_irq_ack | Received |
| 1 | 0 | 1 | usr_irq_ack with PBA bit set | Not Received |
| 1 | 1 | 0 | usr_irq_ack with PBA bit set | Not Received |
| 1 | 1 | 1 | usr_irq_ack with PBA bit set | Not Received |