IRQ Block User Vector Number (0x80) - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2025-05-29
Version
2.0 English

If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In legacy interrupts, only the two LSBs of each field should be used to map to INTA, B, C, or D.

Table 1. IRQ Block User Vector Number (0x80)
Bit Index Default Access Type Description
28:24 5’h0 RW

vector 3

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[3].
20:16 5’h0 RW

vector 2

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[2].
12:8 5’h0 RW

vector 1

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[1].
4:0 5’h0 RW

vector 0

The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[0].