Config Block Registers (0x3) - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2025-05-29
Version
2.0 English

The Config Block registers are described in this section.

Table 1. Config Block Register Space
Address (hex) Register Name
0x00 Config Block Identifier (0x00)
0x04 Config Block BusDev (0x04)
0x08 Config Block PCIE Max Payload Size (0x08)
0x0C Config Block PCIE Max Read Request Size (0x0C)
0x10 Config Block System ID (0x10)
0x14 Config Block MSI Enable (0x14)
0x18 Config Block PCIE Data Width (0x18)
0x1C Config PCIE Control (0x1C)
0x40 Config AXI User Max Payload Size (0x40)
0x44 Config AXI User Max Read Request Size (0x44)
0x60 Config Write Flush Timeout (0x60)