C2H Channel Interrupt Enable Mask (0x90) - C2H Channel Interrupt Enable Mask (0x90) - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID: PG344
Release Date: 2025-05-29
Version: 2.0 English

Table 1. C2H Channel Interrupt Enable Mask (0x90)
Bit Index	Default	Access Type	Description
23:19	5’h0	RW	im_desc_error[4:0] set to 1 to interrupt when corresponding Status.Read_Error is logged.
13:9	5’h0	RW	im_read_error[4:0] set to 1 to interrupt when corresponding Status.Read_Error is logged.
8:7			Reserved
6	1’b0	RW	im_idle_stopped set to 1 to interrupt when the Status.Idle_stopped is logged.
4	1’b0	RW	im_magic_stopped set to 1 to interrupt when Status.Magic_stopped is logged.
2	1’b0	RW	im_descriptor_completd set to 1 to interrupt when Status.Descriptor_completed is logged.
1	1’b0	RW	im_descriptor_stopped set to 1 to interrupt when Status.Descriptor_stopped is logged.
0			Reserved