Block Automation for DMA IP with PL-PCIe Controller - 2.0 English - PG344

You can add the DMA soft IP to the IP integrator canvas and enable block automation for PL-PCIe, as shown in the following figure:

Figure 1. DMA IP Configuration

In this scenario, block automation uses the PCIe Versal device. During block automation, the PCIe Versal device is configured with the chosen Link Width and Link Speed, while the remaining PCIe attributes are set according to the QDMA/XDMA configuration.

Following the PCIe Versal IP configuration, block automation executes PCIe Versal block automation, which subsequently adds the PCIe PHY Versal device. This process triggers PCIe PHY block automation, adding necessary blocks such as the GT Wizard and GT reference clock buffer, and eventually connecting the PCIe PHY with GT and PCIe IP. When all blocks are added, the QDMA/XDMA block interfaces connect to the PCIe Versal device, as shown in the following figure:

Figure 2. IP Interface Connections