AXI4 Memory Mapped Master Bypass Read Interface Signals - AXI4 Memory Mapped Master Bypass Read Interface Signals - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document ID
PG344
Release Date
2025-05-29
Version
2.0 English
Table 1. AXI4 Memory Mapped Master Bypass Read Interface Signals
Signal Name Direction Description
m_axib_rdata

[DATA_WIDTH-1:0]

 I Master read data.

m_axib_rid

[ID_WIDTH-1:0]

 I Master read ID.
m_axib_rresp[1:0] I Master read response.
m_axib_rlast I Master read last.
m_axib_rvalid I Master read valid.
m_axib_rready O Master read ready.
m_axib_ruser

[DATA_WIDTH/8-1:0]

 I Parity ports for read interface. This port is enabled only in Propagate Parity mode.