AXI4-Lite Slave Register Space - AXI4-Lite Slave Register Space - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document_ID
PG344
Release_Date
2026-07-22
Version
2.0 English
Table 1. AXI4 -Lite Slave Register Space
Register Space AXI4-Lite Slave Register Space Description
Bridge registers AXI-4Lite Slave address bit[28] = 0

This is ECAM space. In AXI-Bridge EP mode this space is reserved.
DMA registers AXI-4Lite Slave address bit[28] = 1 This is a QDMA Q space access, in AXI-Bridge mode this space is reserved.