AXI4-Lite Slave CSR Register Space - AXI4-Lite Slave CSR Register Space - 2.0 English - PG344

Versal Adaptive SoC DMA and Bridge Subsystem for PCI Express Product Guide (PG344)
Document_ID
PG344
Release_Date
2026-07-22
Version
2.0 English
Table 1. AXI4 -Lite Slave CSR Register Space
Register Space AXI4-Lite CSR Register Space Description
Bridge registers AXI4-Lite CSR address bit[15] = 0

0x00 to 0xDFF is reserved. Bridge register start at 0xE00. See Register Reference File.
DMA registers AXI4-Lite CSR address bit[15] = 1 This is QDMA Register space and in AXI-Bridge mode this is reserved.