SRIOV VF BARs Tab - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

The SRIOV Base Address Registers (BARs) set the base address register space for the Endpoint configuration. Each BAR (0 through 5) configures the SR-IOV BAR aperture size and SR-IOV control attributes.

Figure 1. SRIOV BARs Tab, Advanced Mode
Table 1. Example Virtual Function Mappings
Physical Function Virtual Function Function Number Range
PF0 VF0 64
PF0 VF1 65
PF1 VF0 68
PF1 VF1 69
PF1 VF1 70
SRIOV Base Address Register Overview
In Endpoint configuration, the core supports up to six 32-bit BARs or three 64-bit BARs. In Root Port configuration, the core supports up to two 32-bit BARs or one 64-bit BAR. SR-IOV BARs can be one of two sizes:
32-bit BARs
The address space can be as small as 16 bytes or as large as 3 gigabytes. Used for memory to I/O.
64-bit BARs
The address space can be as small as 128 bytes or as large as 256 gigabytes. Used for memory only.

All SR-IOV BAR registers have these options:

Checkbox
Click the checkbox to enable the BAR; deselect the checkbox to disable the BAR.
Type
SR-IOV BARs can be either I/O or Memory.
I/O
I/O BARs can only be 32-bit; the Prefetchable option does not apply to I/O BARs. I/O BARs are only enabled for a Legacy PCI Express Endpoint.
Memory
Memory BARs can be either 64-bit or 32-bit and can be prefetchable. When a BAR is set to 64-bits, it uses the next BAR for the extended address space and makes the next BAR inaccessible.
Size
The available size range depends on the PCIe device/port type and the type of BAR selected. The following table lists the available BAR size ranges.
Table 2. SRIOV BAR Size Ranges for Device Configuration
PCIe Device / Port Type BAR Type BAR Size Range
PCI Express Endpoint 32-bit Memory 128 bytes – 2 gigabytes
64-bit Memory 128 bytes – 8 exabytes
Legacy PCI Express Endpoint 32-bit Memory 16 bytes – 2 gigabytes
64-bit Memory 16 bytes – 8 exabytes
I/O 16 bytes – 2 gigabytes
Prefetchable
Identifies the ability of the memory space to be prefetched.
Value
The value assigned to the BAR based on the current selections.
Managing SRIOV Base Address Register Settings
Memory, I/O, Type, and Prefetchable settings are handled by setting the appropriate Customize IP dialog box settings for the desired base address register.

Memory or I/O settings indicate whether the address space is defined as memory or I/O. The base address register only responds to commands that access the specified address space. Generally, memory spaces less than 4 KB in size should be avoided. The minimum I/O space allowed is 16 bytes. I/O space should be avoided in all new designs.

A memory space is prefetchable if there are no side effects on reads (that is, data is not destroyed by reading, as from RAM). Byte-write operations can be merged into a single double-word write, when applicable.

When configuring the core as an Endpoint for PCIe (non-Legacy), 64-bit addressing must be supported for all SR-IOV BARs (except BAR5) that have the prefetchable bit set. 32-bit addressing is permitted for all SR-IOV BARs that do not have the prefetchable bit set. The prefetchable bit related requirement does not apply to a Legacy Endpoint. The minimum memory address range supported by a BAR is 128 bytes for a PCI Express Endpoint and 16 bytes for a Legacy PCI Express Endpoint.

Disabling Unused Resources
For best results, disable unused base address registers to conserve system resources. Disable base address register by deselecting unused BARs in the Customize IP dialog box.
Copy PF0
When set, the Copy PF0 option allows you to set all BAR settings of the remaining PF groups to the same values as PF0 group. Applicable when there are more than one total Physical Function (PF).