Run Block Automation in IP Integrator - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English
To run block automation:
  1. In the Flow Navigator, select Create Block Design.

  2. Add the pcie_versal IP to your block design.

  3. Configure the pcie_versal core by double-clicking on pcie_versal block in your block design (BD). For more information, see Customizing and Generating the Core.

  4. Click Run Block Automation, and click OK.

  5. A pcie_versal_support block is generated.

  6. The PHY IP and GT quads are in the generated Vivado IP integrator design pcie_versal_support along with the helper blocks for reset and clock, as seen in the following figure. For more details, see Example Design.

Note: If changes are made to the PCI Express core block, the supporting GT Wizard and PHY IPs must be deleted, and the block automation steps should be repeated.
Note: GT Quad locations can only be set using user constraints in the Xilinx Design Constraints (XDC) file. For more information, see GT Locations.