Connecting the Core - 1.0 English

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document ID
PG343
Release Date
2024-05-30
Version
1.0 English

This section includes information about using AMD tools to connect the PCI Express core block to the supporting GT Wizard and PHY IPs in the AMD Vivado™ Design Suite.

Unlike AMD UltraScale+™ devices, the GT Wizards and PHY IPs for the AMD Versal™ Adaptive SoC are found outside of the PCIe IP core instead of under the PCIe hierarchy. You have the following two options to generate the two cores and connect them to the PCIe IP core:

  1. You can manually instantiate the IPs within a Block Design, configure them and connect them to the PCIe IP core. For more information about configuring and connecting the PHY and GT Wizard IPs, see Versal Adaptive SoC PCIe PHY LogiCORE IP Product Guide (PG345) and Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
  2. Alternatively, you can let AMD Vivado™ run block automation to automatically instantiate, configure, and make connections for the two cores based on the settings in your PCIe core configuration.