| Name | I/O | Width | Description |
|---|---|---|---|
| phy_txdetectrx | O | 1 | Tells the PHY to perform receiver detection when this
signal is High and POWERDOWN is in P1 low power state. Receiver
detection is complete when phystatus asserts for one pclk cycle. The
status of receiver detection is indicated in rxstatus when phystatus is
High for one pclk cycle.
|
| phy_txelecidle | O | 1 | Forces the tx[p/n] to electrical idle when this signal is High. During electrical idle, tx[p/n] are driven to the DC common mode voltage. Per lane. |
| phy_txcompliance | O | 1 | Sets the running disparity to negative when this signal is logic High. Used when transmitting the PCIe compliance pattern. Per lane. |
| phy_rxpolarity | O | 1 | Requests the PHY to perform polarity inversion on the received data when this signal is High. Per lane. |
| phy_powerdown[1:0] | O | 2 | Requests PHY to enter power saving state or return to
normal power state. Power management is complete when PHYSTATUS asserts
for one PCLK cycle.
|
| phy_rate[1:0] | O | 3 |
Request the PHY to perform a dynamic rate change. Rate change is complete when PHYSTATUS asserts for one PCLK cycle. rxvalid, rxdata, and rxstatus must be ignored while the PHY is in rate change. For AMD Versal™ premium device, 3 bits are valid, while only 2 bits are valid for AMD Versal™ Prime adaptive SoC. AMD Versal Prime adaptive SoC
AMD Versal Premium adaptive SoC
In the simulation mode (PHY_SIM_EN = TRUE), PHY status assertion takes about 45 us for Gen3 speed change. |