Basic Tab - Basic Tab - 1.1 English - PG343

Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343)

Document_ID
PG343
Release_Date
2026-08-07
Version
1.1 English

The following figure shows the initial customization page, used to set the Basic mode parameters.

Figure 1. Basic Tab
Mode
Allows you to select the Basic or Advanced mode configuration of the core.
Device/Port Type
Indicates the PCI Express logical device type.
Maximum Link Width
The core requires the selection of the initial lane width. Wider lane width cores can train down to smaller lane widths if attached to a smaller lane-width device.
AXI-ST Interface Frequency
Enables you to specify the AXI-ST Interface frequency.
AXI-ST Interface Width
The core allows you to select the Interface Width. The default interface width set in the Customize IP dialog box is the lowest possible interface width.
AXI-ST Alignment Mode
When a payload is present, there are two options for aligning the first byte of the payload with respect to the datapath. The options are provided to select the CQ/CC and RQ/RC interfaces.
AXI-ST CQ/CC Frame Straddle and AXI-ST RQ/RC Frame Straddle
When 512-bit AXI-ST interface width is selected AXI-ST frame Straddle is supported for CQ, CC, RQ, and RC AXI-ST interfaces. Option to select CQ and CC AXI-ST frame straddle together and for RQ and RC interfaces.
Enable Client Tag
Enables you to use the client tag.
Enable External PIPE Interface
When selected, this option enables an external third-party bus functional model (BFM) to connect to the PIPE interface of integrated block for PCIe. For details, see PIPE Mode Simulation Using Integrated Endpoint PCI Express Block in Gen3 x8 and Gen2 x8 Configurations (XAPP1184). Refer to these designs to connect the External PIPE Interface ports of the AMD Versal™ device core to third-party BFMs.
Enable RX Message Interface
The core provides a separate receive message interface which the user application can use to receive indications of messages received from the link.
GT Control/Status Ports
Ports used to debug transceiver related issues, must be driven in accordance with the appropriate GT user guide.
GT Wizard Implementation
Selects the GT Wizard IP Flow for GT instantiations. The Legacy GT Wizard is the IP integrator focused flow, it facilitates migrating existing designs. The GT Wizard Subsystem is the new flow that can be used in either IP integrator or RTL for new designs. For assistance in migrating designs to the GT Wizard Subsystem, see AR 000037037.
Note: Starting Vivado 2025.1 release, the default selection of GT Wizard Implementation is changed to GT Wizard Subsystem.