|
Core Specifics |
| Supported Device Family(1)
|
UltraScale+™
,
UltraScale™
, 7 series
FPGA, and
Zynq®-7000 SoC
|
| Supported User Interfaces |
AXI4 and AXI3
|
| Resources |
N/A |
| Provided with
Core
|
| Design Files |
SystemVerilog |
| Example Design |
N/A |
| Test Bench |
N/A |
| Constraints File |
N/A |
| Simulation Model |
Unencrypted SystemVerilog |
| Supported S/W Driver |
N/A |
| Tested Design Flows(2)
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado
|
| Support |
| Provided by Xilinx
at the Xilinx Support web page
|
- For a complete list of supported devices, see the Vivado IP catalog.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|