HDMI 1.4 and 2.0 protocols use three GT channels in a Quad, leaving one unused.
The fourth GT channel can be enabled and used as the TX TMDS clock source instead of
being generated by DCM (MMCM or PLL). This is done by checking the HDMI GT Controller core customization screen option,
Use Fourth GT Channel as TX TMDS Clock. The
gt_tx3
interface port must be connected to the GT
Wizard’s TX3_GT_IP_Interface
. Ensure that the Number of
TX Lanes is four in the GT Wizard customization screen. For HDMI 2.1, the fourth GT
channel is used as the TX TMDS clock source by default.
When this option is enabled, the TX TMDS Clock ports,
tx_tmds_clk_p/n
output ports are disabled.
A pattern generator module is added in the HDMI GT Controller architecture to generate the specific pattern needed to generate the required TMDS clock frequency from the fourth GT channel. The pattern generator control register is located at offset 0x340 and is programmed based on the line rate to TMDS clock ratio. The pattern generator supports ratios of 10, 20, 30, 40, and 50. For example, in a typical HDMI 1.4 resolution such as 1080p60, the line rate per channel is 1.485 Gbps and the TMDS clock is 148.5 MHz, thus giving a ratio of 10. For low line rate resolutions such as 480P60 that need an oversampling technique (for example, x3) to be transmitted, the ratio is computed as the actual line rate per channel (270 Mbs x 3) over TMDS clock (27 MHz), which gives a ratio of 30. For HDMI 2.0 resolutions such as 4KP60, the line rate is 5.94 Gbps and the TMDS clock is 148.5 MHz, thus giving a ratio of 40.
In four channel FRL mode, the fourth GT channel is also used to transmit FRL data. Multiplexing between TMDS clock pattern and FRL data is automatically and internally handled by the HDMI PHY Controller and its software driver, depending on the operating mode. Additional device LUTs and flip-flops are consumed when the fourth GT Channel is enabled as the TX TMDS clock source. Be aware of these additional resources when enabling this option.
MAX FRL Data Rate | 12 Gbps 4 Lanes | 10 Gbps 4 Lanes | 8 Gbps 4 Lanes | 6 Gbps 4 Lanes | 6 Gbps 3 Lanes | 3 Gbps 3 Lanes | TMDS | ||
---|---|---|---|---|---|---|---|---|---|
Device Family | Speed Grade | GT PLL | |||||||
Versal |
|
|
Not Supported | Supported | |||||
|
|
Not Supported | Supported | ||||||
|
|
Supported |