Table 1. TX Initialization Register
Bit |
Default Value |
Access Type |
Description |
Channel 1 |
0 |
0 |
RW |
GTTXRESET |
3:1 |
0 |
RO |
Reserved |
4 |
1 |
RW |
TX_LNKRDY_SB_MASK |
5 |
0 |
RW |
GTTXMSTRESET |
6 |
0 |
RO |
Reserved |
7 |
0 |
RW |
PLL_GT_RESET |
Channel 2 |
8 |
0 |
RW |
GTTXRESET |
11:9 |
0 |
RO |
Reserved |
12 |
1 |
RW |
TX_LNKRDY_SB_MASK |
13 |
0 |
RW |
GTTXMSTRESET |
14 |
0 |
RO |
Reserved |
15 |
0 |
RW |
PLL_GT_RESET |
Channel 3 |
16 |
0 |
RW |
GTTXRESET |
19:17 |
0 |
RO |
Reserved |
20 |
1 |
RW |
TX_LNKRDY_SB_MASK |
21 |
0 |
RW |
GTTXMSTRESET |
23 |
0 |
RW |
PLL_GT_RESET |
Channel 4 |
24 |
0 |
RW |
GTTXRESET |
27:25 |
0 |
RO |
Reserved |
28 |
1 |
RW |
TX_LNKRDY_SB_MASK |
29 |
0 |
RW |
GTTXMSTRESET |
30 |
0 |
RO |
Reserved |
31 |
0 |
RW |
PLL_GT_RESET |