The HDMI GT Controller configuration data is implemented as a set of distributed registers that can be read or written from the AXI4-Lite interface. These registers are synchronous to the AXI4-Lite domain.
Any bits not specified in the following register tables are considered reserved and return zero upon read. The power-on reset values of control registers are zero unless specified in the definition. Only address offsets are listed in the following tables and the base address is configured by the AXI interconnect at the system level.
For more information, see the Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).
| Address (hex) | Register |
|---|---|
| 0x0000 | Version Register (VR) |
| Shared Features and Resets | |
| 0x0014 | Reset (PR) |
| 0x0018 | PLL Lock Status (PLS) |
| 0x001C | TX Initialization (TXI) |
| 0x0020 | TX Initialization Status (TXIS) |
| 0x0024 | RX Initialization (RXI) |
| 0x0028 | RX Initialization Status (RXIS) |
| 0x0068 | GT_DBG_CONTROL (GTDBGC) |
| 0x006C | GT_DBG_STATUS (GTDBGS) |
| Transmitter Functions | |
| 0x0078 | TX Status (TXS) |
| 0x007C | TX Channel Control – Channel 1 and 2 |
| 0x0080 | TX Channel Control – Channel 3 and 4 |
| 0x0084 | TX Channel Control Channel 1 to 4 |
| 0x008C | TX DRIVER Control Extension Channel 1 and 2 |
| 0x0090 | TX DRIVER Control Extension Channel 3 and 4 |
| Receiver Functions | |
| 0x0098 | RX DRIVER Control Extension Channel 1 and 2 |
| 0x009C | RX DRIVER Control Extension Channel 3 and 4 |
| 0x0104 | RX Status (RXS) |
| 0x0108 | RX Equalization and CDR |
| Interrupts Registers | |
| 0x0110 | Interrupt Enable Register (IER) |
| 0x0114 | Interrupt Disable Register (IDR) |
| 0x0118 | Interrupt Mask Register (IMR) |
| 0x011C | Interrupt Status Register (ISR) |
| TXUSRCLK Clocking | |
| 0x0120 | MMCM TXUSRCLK Control/Status (MMCM_TXUSRCLK_CTRL) |
| 0x0124 | DRP CONTROL MMCM TXUSRCLK |
| 0x0128 | DRP STATUS MMCM TXUSRCLK |
| 0x0140 | MMCM RXUSRCLK Control/Status (MMCM_RXUSRCLK_CTRL) |
| 0x0144 | DRP CONTROL MMCM RXUSRCLK |
| 0x0148 | DRP STATUS MMCM RXUSRCLK |
| Clock Detector | |
| 0x0200 | Clock Detector Control Register |
| 0x204 | Clock Detector Status Register |
| 0x0208 | Clock Detector Frequency Counter Timeout |
| 0x020C | Clock Detector Transmitter Frequency |
| 0x0210 | Clock Detector Receiver Frequency |
| 0x0214 | Clock Detector Transmitter Timer |
| 0x0218 | Clock Detector Receiver Timer |
| 0x021C | Clock Detector DRU Frequency |
| 0x230 | Clock Detector Transmitter FRL Frequency |
| 0x234 | Clock Detector Receiver FRL Frequency |
| Data Recovery Unit | |
| 0x0300 | Data Recovery Unit Control Register |
| 0x0304 | Data Recovery Unit Status Register |
| 0x0308 | Data Recovery Unit Center Frequency Low Register – All Channels |
| 0x030C | Data Recovery Unit Center Frequency High Register – All Channels |
| 0x0310 | Data Recovery Unit Gain Register – All Channels |
| TX TMDS Pattern Generator | |
| 0x0340 | Control Register |