Reference Clock Requirements

Reference Clock Requirements - 2.0 English

HDMI GT Controller LogiCORE IP Product Guide (PG334)

Document ID

PG334

Release Date

2024-11-13

Version

2.0 English

The HDMI GT Controller application requires a system clock and a minimum of three GT reference clock inputs for full duplex operation:

System Clock
HDMI TX from an external clock generator
HDMI RX in CDR mode (normal operation)
HDMI 1.4/2.0 RX NI-DRU mode and HDMI 2.1 FRL mode

The system clock should drive the sb_aclk and the axi4lite_aclk. The ports should be connected to a 100 MHz clock. The system clock must be properly buffered (using BUFG) before it is used and connected.

Important: Because the system clock is used by the HDMI GT Controller as the reference clock for the frequency counter in its Clock Detector module, use an oscillator that has a jitter of less than ±40 PPM.

Note the following constraints for the HDMI 1.4/2.0/2.1 reference clock:

The HDMI TX and RX reference clock (Transition Minimized Differential Signaling (TMDS) clocks) input frequency varies according to the input video and both are maximized at 297 MHz. The corresponding input ports need to be constrained at 297 MHz at the Vivado Project top level XDC file for proper timing analysis and closure; that is, create_clock -period 3.367 [get_ports <HDMI TX/RX REFCLK portname>].
The HDMI 2.1 TX and RX reference clock (Transition Minimized Differential Signaling (TMDS) clocks) input frequency varies according to the input video and both are maximized at 297 MHz. The corresponding input ports need to be constrained at 400 MHz for GT Reference clock in the Vivado Project top level XDC file for proper timing analysis and closure; that is, create_clock -period 2.500 [get_ports <HDMI TX/RX REFCLK portname>].
The NI-DRU reference clock frequency can be chosen from two values: 200.00 MHz or 400.00 MHz. The NI-DRU reference clock frequency must be constrained at the Vivado Project top level XDC file at specified frequency; for example, 400 MHz: create_clock -period 2.500 [get_ports <NI-DRU REFCCLK portname>]
Note: The recommended NI-DRU reference clock is 400 MHz.

Note: Although, theoretically a vast range of REFCLK frequencies can be used with NI-DRU, only the indicated frequencies have been tested and characterized per transceiver type. NI-DRU settings, such as gain, were optimized and validated using the indicated frequencies. The REFCLK frequency was selected to support the NI-DRU operation, thereby minimizing the number of REFCLKs needed for full HDMI operation.

The following figure illustrates the full reference clock requirement connections.

Figure 1. HDMI GT Controller Reference Clock Connections

The HDMI TX reference clock comes from an external programmable clock generator capable of generating a range of frequencies from the minimum PLL reference clock (see HDMI TX Oversampled Reference Clock Requirements) to the maximum TMDS clock for supported video formats. For example, the HDMI GT Controller TX uses LCPLL and supports up to 4Kp60 at two pixels per clock. This means the programmable clock generator must be able to generate frequencies from 125 MHz to 297 MHz. For resolutions requiring a lower TMDS clock than the minimum PLL reference clock, the HDMI GT Controller uses the oversampling technique (see the following section for details).

Important: The txrefclk port is accompanied by the tx_refclk_rdy port, which indicates a lock condition. The tx_refclk_rdy port has three requirements:

It is connected to the external clock generator lock pin by default or can be toggled through GPIO. It must be toggled (deasserted then asserted) for every video format change. Alternatively, the TX Frequency Reset bit (bit 3) of the Clock Detector Control register (0x200) can be set if the tx_refclk_rdy port is active.
It can only be asserted when the clock at txrefclk_p/n port is stable.
At AXILITE CLK = 100 MHz, the tx_refclk_rdy minimum hold time is 5 μs.

Failing to meet these requirements causes instability in the system.

TX REFCLK frequency detection is sensitive only to the behavior of the tx_refclk_rdy port, a change that triggers the clock detector to issue the TX frequency change event. The external clock generator is set up for the desired TX clock frequency, which means that the HDMI GT Controller TX should get the requested frequency from the clock generator. Because the assumption is that the HDMI GT Controller gets the correct clock, it only requires the LOCK event to trigger the TX reconfiguration which is represented by the assertion of tx_refclk_rdy.

Note: This mechanism applies only to the TX. The RX is sensitive to the frequency change because there is no user control over the incoming RX TMDS clock.