In FRL mode, the LCPLL dividers are configured to support 3, 6, 8, 10, and 12 Gbps based on a single MGT reference clock frequency (400 MHz).
| FRL Mode (Gbps) | QPLL0 Ref Clk Divider | QPLL0 Multiplier | OUT_DIV | VCO Frequency |
|---|---|---|---|---|
| 3 | 2 | 60 | 4 | 12.0 |
| 6 | 2 | 60 | 2 | 12.0 |
| 8 | 1 | 40 | 2 | 16.0 |
| 10 | 3 | 75 | 1 | 10.0 |
| 12 | 2 | 60 | 1 | 12.0 |