Clock, Reset, and Initialization Ports - 1.0 English

HDMI GT Controller LogiCORE IP Product Guide (PG334)

Document ID
PG334
Release Date
2023-10-18
Version
1.0 English
Table 1. Clocking, Reset, and Initialization Ports
Port Name I/O Clock Domain Description
gt_refclk0_odiv2 I

Available when GT REFCLK0 is selected as one of the input clock sources in the GUI.

Connects to BUFG_GT driven by ODIV2 output port of IBUFDS_GTE

gt_refclk1_odiv2 I

Available when GT REFCLK1 is selected as one of the input clock sources in the GUI.

Connects to BUFG_GT driven by ODIV2 output port of IBUFDS_GTE

gt_refclk2_odiv2 I

Available when GT REFCLK2 is selected as one of the input clock sources in the GUI.

Connects to BUFG_GT driven by ODIV2 output port of IBUFDS_GTE

gt_refclk3_odiv2 I

Available when GT REFCLK3 is selected as one of the input clock sources in the GUI.

Connects to BUFG_GT driven by ODIV2 output port of IBUFDS_GTE

gt_refclk4_odiv2 I

Available when GT REFCLK4 is selected as one of the input clock sources in the GUI.

Connects to BUFG_GT driven by ODIV2 output port of IBUFDS_GTE

gt_refclk5_odiv2 I

Available when GT REFCLK5 is selected as one of the input clock sources in the GUI.

Connects to BUFG_GT driven by ODIV2 output port of IBUFDS_GTE

gt_powergood I Async Connects to GTPOWERGOOD port of the GT Wizard
gt_ch0/1/2/3_ilo_resetdone I Async Connects to CH0/1/2/3_ILORESETDONE ports of the GT Wizard
gt_lcpll0/1_lock I Async Connects to HSCLK0/1_LCPLLLOCK of the GT Wizard
gt_rpll0/1_lock I Async Connects to HSCLK0/1_RPLLLOCK of the GT Wizard
gt_lcpll0/1_reset O Async Connects to HSCLK0/1_LCPLLRESET of the GT Wizard
gt_rpll0/1_reset O Async Connects to HSCLK0/1_RPLLRESET of the GT Wizard
apb_clk I Connect to the free-running clock driving the apb3clk port of the GT Wizard
tx_axi4s_aclk I Transmit Interface Clock
tx_axi4s_aresetn I TXUSRCLK2

Transmit Interface Reset

Unused port. It can be tied High or left unconnected.

rx_axi4s_aclk I Receive Interface Clock
rx_axi4s_aresetn I RXUSRCLK2

Receive Interface Reset

Unused port. It can be tied High or left unconnected.

sb_aclk I

Sideband Interface Clock

Connect to AXI4-Lite clock.

sb_aresetn I

sb_aclk

(AXI4-Lite)

Sideband Interface Reset

Unused port. It can be tied High, left unconnected or connected to the ARESETN port of the PROC_SYS_RESET IP under sb_aclk clock domain.

gt_txusrclk I Connect to the USRCLK output port of the BUFG_GT driving the chN_txusrclk ports of the GT Wizard
gt_rxusrclk I Connect to the USRCLK output port of the BUFG_GT driving the chN_rxusrclk ports of the GT Wizard
axi4lite_aclk I AXI Bus clock
axi4lite_aresetn I AXI4-Lite

AXI Reset. Active-Low.

Must be connected to ARESETN that is synched to axi4lite_aclk port (that is,.peripheral_aresetn port of the Processor System Reset Module IP)

tx_refclk_rdy I Async
Active-High (default):
  • 1 - Locked
  • 0 - Unlocked

TX Reference clock ready or lock indicator. See Reference Clocks Requirements for details about tx_refclk_rdy port implementation.

Active level is controlled by TX RefClk Rdy Active GUI parameter. If set to Low,
  • 1 - Unlocked
  • 0 - Locked
tx_tmds_clk O Single-ended TX TMDS Clock
tx_tmds_clk_p/n O

Differential TX TMDS Clock output

Note: These ports are disabled when GUI option Use Fourth GT Channel as TX TMDS Clock is checked.
tx_video_clk O TX Video Clock
rx_tmds_clk O Single-ended RX TMDS Clock
rx_tmds_clk_p/n O Differential RX TMDS Clock output
rx_video_clk O RX Video Clock