0 |
0 |
RW |
Run: Set this bit to enable clock detector. |
1 |
0 |
RW |
TX Timer Clear – Self Clearing |
2 |
0 |
RW |
RX Timer Clear – Self Clearing |
3 |
0 |
RW |
TX Frequency Reset – Self Clearing when TX Frequency Zero bit
asserts |
4 |
0 |
RW |
RX Frequency Reset – Self Clearing when RX Frequency Zero bit
asserts |
12:5 |
0 |
RW |
Frequency Lock Counter Threshold |
16:13 |
8 |
RW |
Clock detector accuracy range. A high value reduces the accuracy. Increase the
value to get a stable operation when the incoming clock is not of good
quality. |
31:17 |
0 |
RO |
Reserved |