axi4lite_awaddr[9:0] |
I |
Write address |
axi4lite_awprot[2:0] |
I |
Protection type |
axi4lite_awvalid |
I |
Write address valid |
axi4lite_awready |
O |
Write address ready |
axi4lite_awdata[31:0] |
I |
Write data bus |
axi4lite_awstrb[3:0] |
I |
Write strobes |
axi4lite_wvalid |
I |
Write valid |
axi4lite_wready |
O |
Write ready |
axi4lite_bresp[1:0] |
O |
Write response |
axi4lite_bvalid |
O |
Write response valid |
axi4lite_bready |
I |
Response ready |
axi4lite_araddr[9:0] |
I |
Read address |
axi4lite_arprot[2:0] |
I |
Protection type |
axi4lite_arvalid |
I |
Read address valid |
axi4lite_arready |
O |
Read address ready |
axi4lite_rdata[31:0] |
O |
Read data |
axi4lite_rresp[1:0] |
O |
Read response |
axi4lite_rvalid |
O |
Read valid |
axi4lite_rready |
I |
Read ready |
irq |
O |
Interrupt output |
- Clock domain = AXI4-Lite.
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