| Clock | Description |
|---|---|
| core_clk | IP primary clock that is usually connected to qdma/axi_clk. |
| sw_s_axi_lite_aclk | AXI4-Lite clock. All the register accesses work on this clock. |
| Clock | Description |
|---|---|
| core_clk | IP primary clock that is usually connected to qdma/axi_clk. |
| sw_s_axi_lite_aclk | AXI4-Lite clock. All the register accesses work on this clock. |